With the advent of multi-level interconnection schemes in semiconductor wafer processing and as device dimensions are scaled to sub-micron dimensions, the required degree of planarization is increased. This is the result of the stacking of additional layers on top of one another which produces a more rugged wafer topography. Such can result in poor step coverage of metal lines where they cross over high and steep steps. As well, the rugged topography can exceed depth-of-field limitations in photolithography processes, which can require different mask and etch steps for different elevations in the wafer.
Planarization is typically accomplished by etching interlevel isolating dielectric layers, which are typically comprised predominantly of SiO.sub.2. Such techniques include melting and reflow of the dielectric, photoresist-etch-back (REB) and by carefully controlled dielectric deposition techniques which result in a more planar surface. Even with such etch techniques, it is difficult to arrive at a planar upper surface because of a tendency of the low and high regions to etch at the same rate.
Most recently chemical-mechanical polishing (CMP) techniques have been developed which rapidly remove small elevated features without significantly thinning the oxide on the flat or lower areas. CMP processes employ both a chemical and a mechanical component. A rotating or vibrating disk is moved relative to the wafer surface in the presence of a CMP slurry. The slurry includes suspended solids as well as a chemical solution component which attacks the material being polished. The two in combination etch the upper layer of the wafer by chemical and mechanical action which removes the high points much faster than the low points.
CMP is not however without drawbacks. One recognized problem concerns end-point detection during the etch, which is diagrammatically illustrated with reference to FIG. 1. There illustrated is a wafer fragment 10 having field oxide regions 12 and conductive polysilicon runners 14. A first level or layer of insulating dielectric material 16 isolates poly runners 14. An interlevel conductive layer 18 polysilicon is provided atop dielectric layer 16. An isolating dielectric layer 20 is applied atop poly layer 18. Layer 20 has a rugged topography the result of the respective topography of layers 18 and 16. The goal or intent, in this example, is to planarize dielectric layer 20 by a CMP process prior to metallization.
However, a problem of end-point detection renders CMP significantly less accurate than desired. Presently, the degree of dielectric removal with CMP techniques is based solely on time of polishing. Such can result in various degrees of dielectric removal resulting in the end-point being anywhere from as-desired to 3000 Angstroms off. This requires a thicker dielectric layer than would otherwise be required to prevent over-etching. Further, it requires a determination after CMP at which level the planarization stopped, as such impacts subsequent processing steps. Planarization techniques including CMP are described at pages 199-239 and the accompany Errata from Wolf, "Silicon Processing for the VLSI Era", Vol. 2--Process Integration, Lattice Press 1990, which is hereby incorporated by reference.
It would be desirable to overcome these and other problems associated with prior art planarization processes.